Published Paper


Simulation of Double Gate TFET With Different Gate Oxides and Thickness

Chinnala. Pavan Kumar & K.Sivani
Kakatiya Institute of Technology & Science Warangal, Telangana state, India
Page: 163-172
Published on: 2023 June

Abstract

Transistors have changed the world. Everyday our world is progressing by making the electronic devices faster and efficient. Transistors are of two types they are BJT’s and FET’s. FET’s are used for their extensive advantages over BJT[1]. MOSFET’s are well known for their switching speed but compare to MOSFET tunnel FET has many advantages as it provides more switching speed and it performance well with low power applications and low threshold voltage this makes tunnel FET (TFET)  popular over MOSFET. Due to increase in power density it is difficult to continue MOSFET scaling due to sub-threshold swing (SS). One of the best choices to replace the MOSFET for the applications of low power is the TFET[4]. The operation of TFET, it works on the concept of band-to-band tunnelling (BTBT) of electrons. Double gate tunnel field effect transistor overcomes the limitations of leakage current and sub-threshold slope but it also has a drawback of ambipolar behaviour due to its symmetrical source drain architecture, the solution for this is to introduce some asymmetry between source and drain this is through the step channel thickness[3]. The more band-to-band tunnelling of electronics from source to channel it leads to more enhancement in on state current. In this paper different gate oxides, Thickness of oxide are tested, the simulation of double gate tunnel FET will be performed by using cadence software.

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