A Novel Sequence Switching Coding Scheme with L-Decoder Technique for Low Power Consumption in VLSI Design
1 Ch. Likhitha, 2 Dr. Girija SravaniLow power has become a critical design requirement in today's electronics industry, leading to a shift in focus where power dissipation is prioritized alongside performance and area. VLSI systems are now designed for high-speed operation with minimal area to ensure compact and reliable performance. Power optimization at the system level is an active area of research, especially concerning power dissipation in processing units, memories, and communication. A significant portion of power is consumed in data communication over on-chip and off-chip buses. To reduce power consumption, signal encoding techniques have been developed to minimize switching activity on buses, potentially saving up to 70% in power. One notable approach is the use of Hamming coding, such as the "Lagger algorithm," which minimizes transition power during bitsequence transmission by shuffling the bit streams before transmission and regenerating them using a decoder, effectively reducing transitions between '0' and '1'